How AI chips are made

Stage 1 of 14

Chip Design, EDA and IP

Chip design turns an idea for a new chip into a complete blueprint. A chip holds billions of transistors, tiny electrical switches. The blueprint fixes where each one sits and how it is wired to the others. The chip runs on a clock, and a signal has to cross those wires within one tick, less than a billionth of a second. Software from three companies, Synopsys, Cadence and Siemens, lays out the blueprint, checks it and signs it off. A foundry, a factory that makes chips for other companies, accepts only designs that have passed that software’s checks. The foundry prints each layer of the design onto silicon through a stencil called a mask. Changing the blueprint once the masks are made takes new masks and a few months.

• The market for chip design software, simulation software and licensed circuit blocks was about $18 billion in 2025, with Synopsys, Cadence and Siemens EDA holding over 85 percent, counting Ansys as part of Synopsys Source
• Synopsys reported $7.054 billion of revenue for fiscal year 2025, the twelve months to 31 October 2025, of which Ansys contributed $756.6 million after the July close Source

Who leadsSynopsys US·Cadence US·Siemens EDA US

Stage 2 of 14

Silicon and Wafers

Every chip is built on a wafer, a thin round slice of silicon about 30 centimeters across that carries hundreds of chips at once. Making one starts with quartz rock, which is silicon bound to oxygen. The silicon is refined until metal impurities are no more than a few parts per billion. It is then melted, and a small seed crystal is lowered to the surface and drawn slowly back up. The melt freezes onto the seed as one long cylinder, a single crystal with its atoms lined up in one unbroken pattern from end to end. Saws cut the cylinder into discs, and each disc is polished to a mirror finish and made extremely flat across its whole face. In 2025 the top five wafer makers served around 75 percent of the world market, and none of them is American or Chinese.

• China produced 1.50 Mt of polysilicon in 2023, about 93 percent of world output, of which an estimated 98 percent was solar-grade and 2 percent electronic-grade Source
• Electronic-grade silicon was a $1.4 billion market in 2025, with five major suppliers: Wacker, Hemlock, OCI, Tokuyama and Mitsubishi Source

Who leadsShin-Etsu Handotai JP·SUMCO JP·GlobalWafers TW

Stage 3 of 14

Chemicals, Gases and Photoresist

Photoresist is a coating that changes wherever light hits it. A machine spins a coat of it, thinner than a soap bubble, across the wafer. Light shines through a stencil onto the coat, and a liquid wash then takes away the parts the light reached. What remains is a pattern, and the next machine cuts that pattern into the wafer beneath, a step called etching. Hundreds of other chemicals, gases and materials lay down layers, strip them off and clean the wafer between steps. The cleaning chemicals are purified until metal and other impurities are down to parts per trillion, the Japanese chemical maker Sumitomo Chemical said in 2021. A chipmaker has to test and approve each new resist in its own factory before using it. Even a resist that passes the first time takes seven to 17 months to approve, the Semiconductor Industry Association wrote in 2023. Japanese companies held 78 percent of world photoresist sales in 2023, by a Fuji Keizai survey that Japan’s trade ministry reproduced.

• China has controlled gallium exports since August 2023 and accounted for 99 percent of world primary low-purity gallium production, according to USGS in February 2026 Source
• JX Advanced Metals says it holds about 65 percent of the global market for semiconductor sputtering targets as of fiscal 2026 Source

Who leadsJSR JP·Tokyo Ohka Kogyo JP·Air Liquide FR

Stage 4 of 14

Lithography

Lithography prints the pattern of a circuit onto the wafer. A machine holds a stencil of one layer of the circuit up to a light source and projects the image, four times smaller, onto the silicon. The shorter the wavelength of the light, the finer the lines a machine can print. Even so, a machine can print lines narrower than its light’s wavelength. Immersion scanners, for example, shine the light through a layer of water between lens and wafer, which lets them print smaller features with the same light. ASML rates one of its immersion scanners, the NXT:2150i, at features of 38 nanometers or less, printed with argon fluoride laser light at 193 nanometers. Air soaks up extreme ultraviolet light, the shortest in use, so machines that print with it work in a vacuum. Only ASML, a Dutch company, makes them. Export controls are government rules on who a company may sell to. Every advanced chip passes through ASML’s machines, so export controls on ASML affect all advanced chipmaking.

• ASML is the only company that makes extreme ultraviolet (EUV) scanners Source
• ASML sold 48 EUV systems in 2025, versus 44 in 2024 Source

Who leadsASML NL·Canon JP·Nikon JP

Stage 5 of 14

Photomasks and Pellicles

A photomask is the stencil that lithography prints from, at least one for each layer of a chip. The same mask prints its layer on wafer after wafer, so one mask shapes millions of chips. The most complicated layers are printed with extreme ultraviolet (EUV) light, and the rest can often be printed with deep ultraviolet light. For deep ultraviolet the mask is a quartz plate that the light shines through. No glass lets EUV light through, so the mask for EUV layers is a mirror. The mirror is built up from about forty pairs of thin layers, and the light bounces off it. Japan’s AGC and Hoya are two of the three firms that make these mirrors. A dark pattern drawn on top of the mirror soaks up the light wherever no line should print. Any speck of dust on the mask repeats on every wafer it prints. So a thin membrane on a frame, called a pellicle, sits just above the mask and catches dust where it is too far out of focus to print.

• AGC says it is one of three companies worldwide that supply photomask blanks for EUV lithography, and the only one that handles every material and process itself. In December 2024 it said its EUV blank sales grew 50 percent in 2023 Source
• Hoya says it holds an exceptionally high share of the mask blank market, and that customers may gradually start buying EUV blanks from more than one supplier Source

Who leadsAGC JP·Hoya JP·Lasertec JP

Stage 6 of 14

Deposition and Etch

Deposition and etch build the chip itself, one layer at a time. Deposition lays down a thin film, sometimes only a few atoms thick. Lithography prints a pattern on it. Etch then eats away everything the pattern does not protect, and the next film goes down on top. Making one chip takes 1,000 to 1,500 steps, the Semiconductor Industry Association estimated in 2025. Some of the holes the etch cuts in memory chips are more than 50 times deeper than they are wide, like a finger-wide shaft about a meter deep. The film has to coat them right to the bottom. The etch has to eat one material and leave the one beside it untouched. Applied Materials and Lam Research in the United States, Tokyo Electron in Japan and ASM International in the Netherlands make most of these machines. Chinese toolmakers have gained share in both kinds of tool since 2019.

• Between 2019 and 2024 China-based suppliers went from 2 to 7 percent of deposition tools and from under 3 to almost 9 percent of etch and clean tools, by CSET’s analysis of TechInsights data Source
• Tokyo Electron’s own fiscal 2026 results presentation, citing Gartner, puts its world share in calendar 2025 at 23 percent of dry etch, 38 percent of tube and low-pressure CVD and 15 percent of ALD, against 91 percent of coater/developers Source

Who leadsApplied Materials US·Lam Research US·Tokyo Electron JP

Stage 7 of 14

Metrology and Inspection

Metrology (measurement) and inspection are a chip factory’s quality control. Between the steps that build a chip, another machine looks the wafer over. It checks whether the lines are the right width, whether this layer landed squarely on the last one, and whether a speck of dirt has killed a circuit. The main chip in an AI accelerator, the one that does the calculating, is one of the largest cut from a wafer. A bigger chip is a bigger target for a speck. In a textbook example with the same density of specks, 49.2 percent of chips 1 centimeter on a side come out flawless, but only 11.3 percent of chips 2 centimeters on a side. In 2025 one American firm, KLA, held 56.8 percent of the market for these tools, by CSET’s count from TechInsights data. So most of the tools that a chip factory, or fab, uses to find faults come from KLA.

• CSET’s Supply Chain Explorer puts KLA at 56.8 percent of a $15.7 billion process control tool market in 2025, ahead of Applied Materials at 11.2 percent and Lasertec at 6.4 percent Source
• KLA says its process control share grew 360 basis points from 2021 to 2025 and is about 7 times the nearest competitor Source

Who leadsKLA US·Applied Materials US·Lasertec JP

Stage 8 of 14

Foundries and Fabs

A chip factory, or fab, builds the transistors, the billions of tiny switches in every chip, and then wires them together. Each switch works like a valve. Current runs along a narrow strip of silicon called the channel, and a small voltage on a gate above the strip opens or shuts the flow. For decades chipmakers made the strips shorter, so the transistors switched faster and more of them fit on a chip. But once the strip gets short enough, current leaks through even when the gate is off, and the chip burns power doing nothing. The newest kind of transistor, called gate-all-around, cuts this leak by wrapping the gate around all four sides of the strip. A chipmaker needs two things to make the newest chips, and having one does not bring the other. The first is the know-how to build the newest switches, a long sequence of steps that have to run in exact order. In 2026 only TSMC, Intel and Samsung had it. The second is factories that cost tens of billions of dollars each, and in 2022 most of the world’s capacity for the most advanced logic chips was in Taiwan. China’s SMIC runs factories, but without EUV machines or the know-how for the newest switches, its most advanced chips are 7 nm-class. IBM developed 2 nm technology, but it yields no chips until Rapidus finishes a factory to run it, with mass production planned for 2027. No chip company sells enough of one product to fill such a factory on its own, so chip companies share a handful of them, run by foundries that make chips for other companies. TSMC runs the biggest, and all six of its largest plants are in Taiwan.

• TSMC, Intel and Samsung build gate-all-around nodes with EUV lithography, while China’s SMIC builds 7 nm-class nodes without it Source
• 7 nm and below was 79 percent of TSMC’s wafer revenue in 3Q26, on revenue of $46.72 billion at a 66.4 percent gross margin Source

Who leadsTSMC TW·Intel US·Samsung Foundry KR

Stage 9 of 14

Memory and HBM

High bandwidth memory, or HBM, is where an AI chip keeps the numbers it is working on, and it is built to hand them over fast. A memory maker etches tiny holes into each memory wafer, fills them with copper and grinds the wafer until the copper shows through its back. It tests each of the wafer’s chips and stacks up to sixteen good ones into a cube, with every layer wired to the ones below. The cube then sits beside the processor, the chip that does the calculating. Stacking is the hard part because each chip is ground thinner than a human hair and the finished cube has to stay within a height limit of less than a millimeter. One chip that fails after stacking can scrap the whole cube. Only SK hynix, Samsung and Micron make HBM in volume. One US export rule covers HBM from all three, including the two based in South Korea.

• SK hynix’s July 2026 US prospectus, citing IDC, splits 2025 HBM revenue between SK hynix at 63.2 percent, Samsung at 19.3 percent and Micron at 17.4 percent Source
• Micron forecast in December 2025 that the HBM market would grow about 40 percent a year through 2028, from about $35 billion in 2025 to around $100 billion in 2028 Source

Who leadsSK hynix KR·Samsung KR·Micron US

Stage 10 of 14

Advanced Packaging

Packaging joins finished chips into one component and mounts them on a small circuit board, called a substrate, wired far more coarsely than the chips themselves. A lithography machine, which prints a chip’s circuits, can cover only a rectangle about the size of a postage stamp in one shot. Many leading accelerators, Nvidia’s Blackwell among them, need more logic than fits in that rectangle. So they are built from several chips, called dies, set side by side on an interposer, a layer of much finer wiring that links them and sits on the substrate. Stacks of memory chips sit on the same interposer, a few millimeters away. The interposer is either one piece of silicon or layers of fine copper wiring that often carry small silicon bridges where the links are densest. Silicon expands less than the resin substrate beneath it when heated, so the package can warp and its joints crack. Preventing that in high volume is hard. Nvidia, Google, AMD and Amazon all use TSMC’s interposer packaging, called CoWoS, made in Taiwan.

• Epoch AI estimates Nvidia used 60.3 percent of the world’s CoWoS packaging capacity in 2025, with a 90 percent confidence interval of 56.5 to 64.3. It estimates that Nvidia, Google, AMD and Amazon together used around 90 percent of CoWoS capacity, but only about 12 percent of advanced logic die production Source
• On the July 2026 earnings call, Wei said TSMC’s packaging capacity was so tight that it limited customers’ growth, and that back-end capacity was still in shortage Source

Who leadsTSMC TW·Intel US·ASE Technology TW

Stage 11 of 14

Substrates and PCBs

A package substrate is the adapter between a chip and the circuit board under it. The chip’s connections are finer than a human hair, but the board is wired in millimeters. The substrate is built in layers, like plywood, around a stiff core of glass cloth and resin. Thin sheets of epoxy film are pressed onto both faces of the core. A laser burns holes through each sheet, and copper plated into the holes carries signals from one layer to the next. Every added layer is another set of holes that can fail. A handful of firms build these substrates, and two of the materials inside them come mainly from Japanese makers. Ajinomoto dominates the film, and Nitto Boseki dominates the low-expansion glass cloth in the core.

• Ajinomoto told investors in June 2026 that its build-up film has held over 95 percent of its market since its launch Source
• Ibiden told investors in May 2026 that it typically takes close to 100 percent of each new generation of interposer-type substrates at launch. That share may decline by 20 to 30 percent after about three to six months. Ibiden expects to keep its technological advantage in silicon-bridge substrates at least through fiscal 2030 Source

Who leadsAjinomoto JP·Nitto Boseki JP·Ibiden JP

Stage 12 of 14

Test and Assembly

Before a chip can be sold, a machine called a tester has to check that it works. While the chips are still on the wafer, thousands of needles press onto small metal pads on each one. The tester sends signals through the needles and reads what comes back, and any chip that fails goes no further. A modern AI accelerator is a dozen expensive pieces bonded into one package, and if one piece is bad, all of them are thrown away. So the industry now tests chips earlier, at higher temperatures and for longer, to make weak ones fail during testing before they reach a finished product. Two firms, Advantest in Japan and Teradyne in the United States, sell most of the testers.

• Advantest estimates that it held about 65 percent of the tester market by value in calendar 2025. It puts its share of system-on-chip (SoC) testers at 66 percent, up about 10 points in a year, and of memory test at about 60 percent Source
• The tester market was about $9.0 billion in calendar 2025: $6.9 billion of SoC testers, up about 68 percent year on year, and $2.1 billion of memory testers Source

Who leadsAdvantest JP·Teradyne US·ASE TW

Stage 13 of 14

Systems and Networking

One AI chip is not enough to train a model. So seventy-two of them are wired together in a rack, a cabinet the size of a wardrobe, and run as one computer. Many such racks are then linked to train a large model. Each chip sits on its own board and draws more than a thousand amps, several times the current a whole house is wired to carry. The chips have to swap results with each other all the time. A copper wire can carry those signals only a few meters before they fade, so the longer links send them as light down glass fiber. Many companies can build the rack, but in 2026 the lasers that send the light were scarce.

• In 2025 China produced about 70 percent of the world’s indium, the raw material for indium phosphide lasers, and it put indium under new export restrictions in February 2025 Source
• NVLink 6 carries 3,600 GB/s per GPU and a Vera Rubin NVL72 rack moves 260 TB/s, by Nvidia’s Rubin launch release of January 2026 Source

Who leadsNvidia US·Broadcom US·Foxconn TW

Stage 14 of 14

Data Centers and Power

A data center feeds electricity to the machines inside it and carries away the heat they give off. One rack of AI chips, a cabinet taller than a door, can draw 142 kilowatts. Every watt of it comes back out as heat, and liquid piped through the rack carries the heat away. A large training site already holds more than a hundred thousand chips. The newest sites are planned in gigawatts. One gigawatt is the whole output of a large power station, and Epoch AI projects that OpenAI’s seven Stargate sites in the United States will add up to more than nine of them by 2029. Getting that much electricity to the site is harder than putting up the building. Transformers and heavy switches connect a site to the grid, and turbines make the power. All of them come from a few suppliers and take years to arrive.

• In 2024, large power transformer lead times of 36 months were commonly quoted, and the longest reached 60 months. Before the pandemic an order took under a year, and 82 percent of the units put into US service in 2019 were imported Source
• Measured by capacity, US producers supplied 29.2 percent of the large power transformers of 60 MVA and above bought in the US in 2023, down from 32.5 percent in 2021. Their lead times averaged three years in 2023, against one and a half years for importers Source

Who leadsGE Vernova US·Hitachi Energy CH·Siemens Energy DE

Chapter 15

The Economics of AI Chips

Most of what it costs to build Nvidia’s B200, an AI chip from its Blackwell line, goes to memory and packaging that a few firms supply. A bill of materials is the list of parts inside a product and what each one costs. Epoch AI estimated in December 2025 that the B200 cost about $6,400 to build. The two logic dies, the pieces of silicon that do the calculating, cost about $900 of that. The stacked memory beside them accounted for about half, and the packaging that wires the dies and memory together cost more than the dies. Three firms, SK hynix, Samsung and Micron, dominate the world market for that memory. One Taiwanese firm, TSMC, does that packaging.

• Epoch AI estimated in December 2025 that a B200 cost about $6,400 to build, within a range of $5,700 to $7,300. Reports in March 2024 put its selling price at $30,000 to $40,000 per chip Source
• In that estimate memory was half the cost, $2,900 for 192 GB of HBM3E at $14 to $17 per gigabyte. The logic dies cost $900 Source

Chapter 16

Who Controls the Chain

Export controls work only when a country’s own firms sell something the buyer cannot get elsewhere, so few governments can use them to much effect. An export control is a rule that requires the government’s permission for a sale. The government names an item and a country or a buyer. From then on its own companies must hold a license before they ship that item to that country or buyer. The American government extends some of these rules to goods made abroad with American technology. The machines, software and chemicals used to make an advanced chip come from a short list of firms in the United States, the Netherlands and Japan, so those three governments can control who gets them.

• Taiwan held 69% of the world’s logic chipmaking capacity below 10 nm in 2022 and South Korea 31%, on the Semiconductor Industry Association and Boston Consulting Group’s count Source
• Korean suppliers took 82.5% of 2025 high-bandwidth memory revenue (SK hynix 63.2%, Samsung 19.3%) and 76.9% in the first quarter of 2026. The figures come from the market research firm IDC, relayed in SK hynix’s July 2026 US prospectus Source